Registers
🧠Register Set (VIREX VM)
The VIREX virtual machine provides a fixed set of general-purpose and special-purpose registers, each designed to support specific roles such as execution flow, memory management, I/O, or control signaling.
Although some registers are named with specialized roles, as of version 0.5.0, only a few instructions implicitly expect specific registers. This means that in most cases, registers can be used flexibly as general-purpose storage without restriction.
Registers are internally identified by integer IDs.
During assembly, the compile-time functions ref() and val() are used to indicate register intent, whether a reference (address) or value should be used.
- By default, registers are interpreted as references (ref()).
- Instructions like SETR and GETR explicitly require register references, not values.
| ID | Name | Purpose |
|---|---|---|
| 0 | H0 | Label Handler (primary) |
| 1 | H1 | Label Handler (secondary) |
| 2 | I0 | Index register 0 |
| 3 | I1 | Index register 1 |
| 4 | JS | Journal Start / log pointer |
| 5 | KC | Kill Code / exit signal |
| 6 | L0 | Link - Pointer |
| 7 | L1 | Link - Float value |
| 8 | L2 | Link - Integer value |
| 9 | L3 | Link - Unsigned integer value |
| 10 | NX | NeXt Instruction Pointer |
| 11 | OP | Output |
| 12 | P0 | Proxy Counter 0 |
| 13 | P1 | Proxy Counter 1 |
| 14 | P2 | Proxy Counter 2 |
| 15 | P3 | Proxy Counter 3 |
| 16 | QT | Quantity |
| 17 | RF | Reference |
| 18 | SP | Stack Pointer |